The present invention relates to the electrical, electronic and computer arts, and, more particularly, to communications technologies, and the like.
As data rates in serial links increase beyond 50 Gb/s, multi-level signaling techniques such as 4-level pulse amplitude modulation (PAM4) are finding increased use in electrical as well as optical serial link applications. A PAM4 communication link transmits 2 bits of information per symbol as compared to more traditional non-return-to-zero (NRZ) modulation schemes (also known as 2-level pulse amplitude modulation, or PAM2).
It is common for input/output (I/O) receiver circuitry used to recover data sent across such a link to support both PAM4 and NRZ modulation schemes with the same symbol rates. A relatively trivial modification to the PAM4 receiver circuitry can support the NRZ data recovery. PAM4 receivers employ at least 3 samplers (or slicers) to detect the PAM4 signaling levels. A common technique for enabling NRZ data recovery using PAM4 receiver (RX) circuitry is to use only the sampler responsible for detecting the most significant bit (MSB) of the PAM4 data. This can be done with only 1 of the 3 samplers, and the other 2 samplers are unused.
Existing solutions for NRZ data detection using a PAM4 receiver rely on information from one sampler. This can have drawbacks due to the limited sensitivity of the single sampler, which can be limited by thermal noise or random offset due to device mismatch. Using larger devices can help in mitigating both the noise and offset, but at the expense of higher power (for the sampler and also clocking power).